During the 2018 TSMC Technology Symposium USA event, Arm’s Physical Design Group introduced its development plans for the Artisan physical IP portfolio on TSMC’s 22nm ultra-low power (ULP) and ultra-low leakage (ULL) process platforms. With an aggressive development schedule and a broad range of IPs, our enthusiasm for accelerating SoC designs has resulted in early access for our mutual customers to explore what the Artisan products and the TSMC 22nm process technologies can achieve for their complex SoC designs.
The initial announcement of the Artisan physical IP for TSMC 22nm ULL and ULP platforms included a key component - a dozen foundry sponsored memory compilers spanning the two TSMC 22nm process nodes. In addition, Arm’s own Artisan standard cell and general purpose I/O (GPIO) libraries are available for these 22nm platforms. Our teams have worked intensively to expedite the library deliverables, which means our customers can start their design evaluations now. Several of our lead silicon partners have already benefited from this close collaboration between Arm and TSMC, and are on their way towards taping out their first ultra-low power SoCs. We will share more exciting updates at Arm TechCon on October 16-18. Come join us!
Derived as an optical shrink from the 28nm HPC+ platform, TSMC’s 22nm ULL and ULP processes offer various options for a broad range of designs. The 22ULP technology offers the power/performance trade-off typically sought after by mobile and consumer applications, while with its ultra-low leakage SRAM (Static Random-Access Memory) and low-voltage logic devices, the 22ULL technology provides significant power reduction crucial for designs in IoT and wearables market segments. TSMC has given partners and customers a direct and simplified migration path from 28HPC+ by choosing to manufacture 22nm as an optical shrink. They can also make a larger geometric jump to see even more benefits when migrating from 40nm or 55nm into one of the two 22nm nodes offered by TSMC. The process technology benefits of TSMC’s 22nm platforms combined with highly optimized Arm Artisan Physical IP can certainly provide a compelling reason for partners and customers to make their next planar node progression.
All Artisan memory compilers for the TSMC 22nm ULP and ULL process technologies are sponsored by TSMC; these compilers are optimized for the low-leakage and low-power requirements of next-generation edge computing devices, providing several power saving features including
Complementary to the memory compilers are ultra-high-density, high-density and high-performance Artisan logic libraries, including Power Management, Retention and High Performance Kits. A featured logic product is the Thick Gate Oxide Library, ideal for low-frequency, always-on blocks for extreme leakage power optimization. The Artisan General Purpose I/O (GPIO) libraries enable the smallest footprint I/O; this single-sized I/O is usable in staggered, in-line, or a dual-row solution. Combined with the widely programmable bidirectional I/O cell, the Artisan GPIO library covers a broad end-application space.
(Note: additional options may be added in future based on market demand)
The planned Arm offering for the TSMC 22nm process has grown since its debut in May and now includes Arm POPTM IP offerings for Cortex-A73 and Cortex-A53 with multiple power, performance and area (PPA) targets and configurations. Our POP IP enables faster time-to-market of Arm compute cores using Artisan logic libraries, customized memory instances, and implementation utilities. The POP IP solution provides optimized results while simplifying integration of the CPU core. For the TSMC 22nm process nodes, the Cortex-A series cores were chosen for the initial POP IPs to enable flexible big.LITTLE implementation. Arm is also proactively pursuing longer-term solutions for the 22nm process nodes to enable our partners and customers to extract the most from the TSMC processes at ultra-low voltages while addressing the various challenges present for any design at these domains.
Arm physical IP platform for TSMC 22nm is available for evaluation now. Come chat with us in booth 708 at TSMC OIP on Oct. 03 at Santa Clara Convention Center. If you can’t make it, contact Arm Physical Design Group.
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